The present invention relates to semiconductor memories having electrically erasable and programmable nonvolatile semiconductor memory cells. More specifically, the present invention is directed not only to a semiconductor memory for recording a plurality of pieces of bit data on a cell basis by setting one of four or more potential levels to each cell but also to an information storage device capable of including a semiconductor memory.
Keeping pace with the development of portable information devices, storage devices using a writable nonvolatile memory as a storage medium are rapidly gaining popularity in recent years.
However, the cost-per-unit-capacity of a storage device using a nonvolatile memory as a storage medium is higher than that of a storage device using a magnetic disk as a storage medium. Therefore, equipment requiring a large storage capacity often employs storage devices using a magnetic disk as a storage medium.
Under these circumstances, there has been a demand for an increased storage capacity in developing nonvolatile-memory-based storage devices.
Multilevel memory technology is a solution to meet this demand.
The multilevel memory technology involves a control over a potential of a floating gate provided in an electrically erasable and programmable nonvolatile semiconductor memory cell so that the potential belongs to one of a plurality of predetermined potential levels.
This technology also identifies a potential stored in a cell by checking which potential level such potential belongs to. Through these operations, a single cell is allowed to deal with multilevel data.
The aforementioned technology thus opens the way to the recording of data consisting of a plurality of bits in a cell unlike conventional technologies that allow only one-bit data to be recorded in a cell. As a result, large-capacity storage can be implemented.
In the multilevel memory technology, the operation of writing data to a cell is performed with considerations given to provide a margin between a desired potential level and a potential level adjacent to the desired potential level by controlling the setting of a potential to a floating gate more finely.
With respect to the reading of data written in a cell, techniques are disclosed in ISSCC95/Feb. 16, 1995/Digest of Technical Papers: Session 7"Flash Memory" TA 7.7 (pp. 132 to 133): A multilevel-Cell 32Mb Flash Memory (INTEL Corporation), and JP-A-4-507320.
In the former technique, the potential level stored in a cell is identified from a plurality of predetermined potential levels through the operation of discriminating the potential stored in the cell (the operation of discriminating one of two levels) performed for a plurality of times. As a result of these operations, data consisting of a plurality of bits written in the cell is determined.
Let us take an example in which two-bit data is written to a single cell by setting the potential to be stored in the cell to one of four levels.
In this example, the four levels are grouped into two. A discriminating operation is performed to determine which group the potential stored in the cell belongs to.
Then, the group to which the potential stored in the cell belongs determined from the result of the discriminating operation is further divided into two subgroups, and another discriminating operation is performed to determine which subgroup the potential stored in the cell belongs to.
As a result of these operations, the level to which the potential stored in the cell belongs is identified from the predetermined four levels. Thus, the two-bit data written to the cell is determined.
On the other hand, in the latter technique, the level to which the potential stored in a cell belongs is identified from a plurality of predetermined levels using a plurality of discriminating means whose discriminating thresholds are different. Through this technique, data consisting of a plurality of bits written to the cell can be determined.
Let us take an example in which two-bit data is written to a single cell by setting the potential to be stored in the cell to one of four levels.
In this example, means for discriminating the first level and the second to fourth levels among the four levels are provided, and means for discriminating the first and second levels and the third and fourth levels are provided, and further means for discriminating the first to third levels and the fourth level are provided. By causing these discriminating means to perform their discriminating operations once, the level to which the potential stored in the cell belongs is identified from the four levels.
Through these operations, the two-bit data written to the cell is determined.
By the way, the read operation involved in the aforementioned multilevel memory technology addresses the following problems.
In the technique in which the level to which the potential stored in a cell belongs is identified from a plurality of predetermined levels through the potential discriminating operation performed for a plurality of times, data consisting of a plurality of bits is determined through the plurality of discriminating operations, and thus the read operation takes time.
The seriousness of this problem increases with increasing number of bits constituting the data to be stored in a single cell. Thus, this problem impairs the high-speed reading performance that is one of the advantages a storage device using a nonvolatile memory as a storage medium has over a storage device using a magnetic disk as a storage medium.
In the technique in which the level to which the potential stored in a cell belongs is identified from a plurality of predetermined levels using a plurality of discriminating means whose discriminating thresholds are different, a plurality of discriminating means must be provided, and thus the area of the chip is disadvantageously increased.
The seriousness of this problem also increases with increasing number of bits constituting the data to be stored in a single cell. That is, if two-bit data is to be stored in a single cell, three discriminating means are required per cell, which means that, if three-bit data is to be stored in a single cell, seven discriminating means are required per cell.
Such disadvantage, which is the increased chip area brought about by the increased number of peripheral circuits, does spoil the advantage, which is the increased storage capacity per array area given by the increased number of bits per cell.